Most memory devices store and retrieve data by addressing specific memory locations. Addressing specific memory locations, however, often becomes the limiting factor for systems that rely on fast memory access. The time required to find an item stored in memory can be reduced considerably if the stored data item can be identified for access by the content of the data itself rather than by its address. Memory that is accessed in this manner is called content-addressable memory (CAM).
Unlike standard random access memory (RAM) in which the user supplies a memory address and the RAM returns the data word stored at that address, a CAM is designed such that the user supplies a data word and the CAM searches its entire memory in one-clock cycle to see if that data word is stored anywhere in it. If the data word is found, the CAM returns a list of one or more storage addresses where the word was found. The CAM can be preloaded at device start-up and rewritten during device operation.
Because a CAM is designed to search its entire memory in a single operation, it is much faster than RAM in virtually all search applications. CAM is therefore ideally suited for functions, such as Ethernet address lookup, data compression, pattern-recognition, cache tags, high-bandwidth address filtering, and fast lookup of routing, high-bandwidth address filtering, user privilege, security, or encryption information on a packet-by-packet basis for high-performance data switches, firewalls, bridges, and routers.
A typical implementation of a static random access memory (SRAM) CAM cell combines six transistors with additional circuitry (e.g. transistors) to perform the one-digit comparison between the memory input and the given cell data. The additional circuitry involves at least three to four additional transistors, hence a very large cell size of eight to ten transistors, hence a costly device. A schematic of a conventional state-of-the-art SRAM-based CAM cell is depicted in FIG. 1. The CAM cell of FIG. 1 is provided as a standard SRAM cell with four or more transistors designed to implement the exclusive-OR (EOR) function.
Unlike a RAM chip, which has simple storage cells, each individual memory bit in a fully parallel CAM has its own associated comparison circuit to detect a match between the stored data bit and the input data bit. CAM chips are thus considerably smaller in storage capacity than regular memory chips. Additionally, match outputs from each cell in the data word can be combined to yield a complete data word match signal. The associated additional circuitry further increases the physical size of the CAM chip. Furthermore, CAM as it is done today (using SRAM elements) is intrinsically volatile, meaning that the data are lost when the power is turned off. As a result, every comparison circuit needs being active on every clock cycle, resulting in large power dissipation. With a large price tag, high power and intrinsic volatility, CAM is only used in specialized applications where searching speed cannot be accomplished using a less costly method.
Attempts to improve standard SRAM-based CAM have been proposed using magnetic storage cells (MRAM). U.S. Pat. No. 6,304,477, for example, discloses a standard multiple transistor SRAM-like CAM to which two magnetic tunnel junctions have been attached. The magnetic tunnel junctions provide non-volatility of the stored data, which is critical both for storing the data as well as for using masking modes architectures.
In another approach set forth in U.S. Pat. No. 6,191,973, a CAM architecture has been proposed using only magnetic (MRAM) cells. In this case, the cell element is a pair of magnetic tunnel junctions (MTJ) in opposite polarity with the input driving one of the gates of the underlying (for each cell) selection transistor. The disclosed scheme provides a significant improvement in density, wherein each CAM cell is formed from only two selection transistors and two magnetic tunnel junctions (2T/2J).
In view of the foregoing, a need exists for improved MRAM storage cells that overcome the aforementioned obstacles and deficiencies of conventional memory storage systems.
It should be noted that the figures are not drawn to scale and that elements of similar structures or functions are generally represented by like reference numerals for illustrative purposes throughout the figures. It also should be noted that the figures are only intended to facilitate the description of the preferred embodiments of the present disclosure. The figures do not illustrate every aspect of the present disclosure and do not limit the scope of the disclosure.